The present invention relates in general to electronic circuits and components therefor, and is particularly directed to a new and improved controllably switched current mirror-based, current-sensing and correction circuit that provides programmable, discrete step compensation for temperature variations of an output switching MOSFET of a buck mode DCxe2x80x94DC converter.
Electrical power for an integrated circuit (IC) is typically supplied by one or more direct current (DC) power sources, such as a buck-mode, pulse width modulation (PWM) based, DCxe2x80x94DC converter of the type diagrammatically shown in FIG. 1. As shown therein, a controller 10 supplies a PWM signal to a (MOSFET gate) driver 20, for controlling the turn-on and turn-off of a pair of electronic power switching devices, to which a load is coupled. In the illustrated DCxe2x80x94DC converter, these power switching devices are depicted as an upper (or high side) power NMOSFET (or NFET) device 30, and a lower (or low side) power NFET device 40, having their drain-source current flow paths connected in series between a pair of power supply rails (e.g., VIN and ground (GND)).
The upper NFET device 30 is turned on and off by an upper gate switching signal UGATE being applied to its gate from driver 20, and the lower NFET device 40 is turned on and off by a lower gate switching signal LGATE from driver 20. A common node 35 between the upper and lower NFETs is coupled through an inductor 50 (which may typically comprise a transformer winding) to a load reservoir capacitor 60 coupled to a reference voltage terminal (GND). A connection 55 between inductor 50 and capacitor 60 serves as an output node from which a desired (regulated) DC output voltage VOUT is applied to a LOAD 65 (shown as coupled to GND).
The output node connection 55 is also fed back to error amplifier circuitry (not shown) within the controller, the error amplifier being used to regulate the converter""s output DC voltage relative to a reference voltage supply. In addition, the common node 35 is also coupled to current-sensing circuitry 15 within controller 10, in response to which the controller adjusts the PWM signal, as necessary, to maintain the converter""s DC output within a prescribed set of parameters.
For this purpose, the controller may incorporate a current-sensing circuit of the type described in U.S. Pat. No. 6,246,220, entitled: xe2x80x9cSynchronous-Rectified DC to DC Converter with Improved Current Sensing,xe2x80x9d issued Jun. 12, 2001, by R. Isham et al, assigned to the assignee of the present application and the disclosure of which is incorporated herein. As described therein, the controller monitors the source-drain current flowing through the lower NFET 40 by way of a current-sensing or scaling resistor 37 electrically interconnected between node 35 and a current-sensing circuit 15.
The current-sensing circuit is operative to monitor the current ISENSE flowing through scaling resistor 37. This current is the product of the output current IOUT flowing from the common node 35 to the inductor 50 times the ratio of the ON-resistance RDS40ON of the lower NFET 40 to the resistance R37 of the scaling resistor 37, and is thus proportionally representative of the output current IOUT. The load current IL, namely the current I50 flowing through the inductor 50, is substantially equal to the output current IOUT minus the current ISENSE flowing through the scaling resistor 37.
As the ratio of RDS40ON to R37 is typically relatively small, the current ISENSE will be substantially smaller than the output current IOUT, so that the output current IOUT and the load current IL will have substantially similar magnitudes, making ISENSE representative of load current. The resistance of the scaling resistor 37 is selected to provide a prescribed value of current flow for the values of load current IL and/or the value of the ON-state resistance RDS40ON of the lower NFET 40. Thus, the sensitivity or magnitude of, for example, voltage droop, current limiting or trip, and current balancing incorporated into the DC/DC converter is effectively xe2x80x98scaledxe2x80x99 by selecting resistor 37 relative to the value of the on-state resistance RDS40ON of the lower NFET 40. The voltage drop across the on-state resistance RDS40ON of the lower NFET 40 (usually negative) is accommodated in the converter without a negative voltage supply. In addition, as the ON-resistance RDS40ON of the lower NFET 40 varies with temperature, scaling resistor 37 may be replaced with a network including a positive temperature coefficient thermistor that has a temperature coefficient which offsets the behavior of NFET 40.
As shown in greater detail in FIG. 2, the controller""s current-sensing circuit 15 comprises a sense amplifier 200 having a first, non-inverting (+) input 201 coupled to a controller SENSExe2x88x92 port 11, and a second, inverting (xe2x88x92) input 202 coupled to a controller SENSE+ port 12. The SENSExe2x88x92 port 11 is coupled to the grounded termination of NFET 40, while the SENSE+ port 12 is coupled through scaling resistor 37 to common node 35. The sense amplifier 200 has its output 203 coupled to the gate 213 of an NFET 210, whose drain-source path is coupled between the SENSE+ port 12 and input terminal 221 of a current mirror 220. The current mirror 220 includes a diode-connected input PFET 230 having its drain and gate coupled in common to input terminal 221 and its source coupled to voltage supply rail VCC. The gate of PFET 230 is coupled in common to the gate of current mirror PFET 240, the source of which is coupled to the supply rail VCC and the drain of which is coupled to an output terminal 222.
In operation, the sense amplifier 200 and NFET 210 (which serves as a controlled impedance) are operative to continuously drive the controller""s SENSE+ port 11 toward ground potential. This forces the end of the current feedback resistor 37 which is connected to controller SENSE+ port 12 to be at ground potential and the end connected to common node 35 to have a negative voltage. The negative voltage at common output node 35 will be equal to the product of the output current IOUT and the on-state resistance RDS40ON between the drain and source of the lower NFET 40.
Current from the current mirror 220 flows into the drain and out of the source of NFET 210 into the SENSE+ port 12. Also flowing into the SENSE+ port 12 from the opposite direction is the current ISENSE which, as described above, is representative of load current IL. In order to maintain the SENSE+ port 12 at ground potential, sense amplifier 200 adjusts the current flowing through NFET 210 and into SENSE+ port 12 to be substantially equal to ISENSE. Since ISENSE is representative of the load current IL, the current flowing through NFET 210 and into SENSE+ port 12, as controlled by sense amplifier 200, is also representative of load current IL. Current mirror 220 mirrors the sensed current flowing through NFET 210 and couples this current via output port 222 to the controller""s error amplifier circuitry that monitors the output node 55.
The on state resistance RDS40ON of the lower NFET 40 may increase by up to forty percent, as the temperature increases in a typical application. If scaling resistor 37, which couples the common node 35 to the SENSE+ port 12 does not also increase at the same rate as RDS40ON, the fed back current will be in error. To correct for this, resistor 37 may be replaced by a network including a positive temperature coefficient thermistor. This may be both complicated and costly.
In accordance with the present invention, the above-discussed temperature variation problem is successfully addressed by a new and improved current-sensing and correction circuit, that provides programmable, step-wise temperature compensation, and is configured to be readily incorporated into a DCxe2x80x94DC converter, such as, but not limited to a buck mode converter architecture of the type shown in FIGS. 1 and 2. The front end portion of the invention includes sense amplifier, NFET and current mirror circuitry of FIG. 2.
To provide the step-wise programmable temperature compensating current adjustment functionality of the invention, the current mirror circuitry of FIG. 2 is augmented with a plurality of controllably switched, auxiliary current mirror output stages, the number of which may be arbitrarily large. The auxiliary current mirror output stages are coupled in parallel with the current mirror output PFET of the front end stage""s current mirror. Each auxiliary current mirror stage contains a current mirror output PFET having its source-drain path coupled in series with that of an associated controllably switched PFET, between a voltage supply rail and a summation current output terminal. The gates of the auxiliary current mirror PFETs are coupled in common with the gate of the front end stage""s current mirror PFET.
When a respective switched PFET is selectively turned-on by a programmed decoder, its associated current mirror output PFET is coupled in parallel with the current mirror output PFET of the front end stage""s current mirror, causing the parallel-coupled PFET to supply an additional mirrored xe2x80x98scalingxe2x80x99 current to the current output terminal, and summed with the output current produced by the front end stage""s current mirror output PFET. This provides the temperature compensation circuit of the invention with its intended current-scaling functionality in the form of linear combinations of the currents mirrored by one or more auxiliary current mirror output PFETs. As non-limiting examples, the xe2x80x98scaledxe2x80x99 output current may be used for xe2x80x98droopxe2x80x99 compensation and over-current detection. The magnitude of the current provided by a respective auxiliary current mirror PFET will depend upon the ratio of its geometry with that of the front end stage""s current mirror input transistor.
In order to control which auxiliary current mirror PFETs provide additional current, the gates of their associated switched PFETs are coupled to decoded output lines of an mxc3x97n decoder. The decoder has m programmable inputs coupled to a programming source and a n programming inputs coupled to a switching device control source unit (temperature sensor). The decoder thus effectively serves as a look-up table, and is operative to map its m and n inputs into a P bit output code, that is applied to the controllably switched PFETs of the auxiliary current mirror stages.
To provide temperature-based current compensation for variations in the drain-source resistance of the lower side MOSFET of a buck mode DCxe2x80x94DC converter, the mapping table stored in the decoder may be defined in accordance with a priori knowledge of the thermal behavior characteristics of the MOSFET and/or by the use of a thermal sensor. The use of programming inputs to the decoder provides the designer with flexibility as to placement of thermal detection components for the monitored lower side MOSFET. Thus, if circuit board area does not allow placement of a thermal detector in relatively close proximity of the converter""s low side MOSFET, any offset between the actual temperature of the component and a relatively proximate monitoring location may be adjusted by an appropriate programming and mapping scheme for the decoder.